Interrupt Control Registers 0, 1 (Intcr0, Intcr1) - Renesas H8S/2158 User Manual

19.3.13 Interrupt Control Registers 0, 1 (INTCR0, INTCR1)

The INTCR registers enable or disable an interrupt.
INTCR0
Bit Bit Name
7 FEIE
6 FFIE
5 DRPIE
4 DTIE
3 CRPIE
2 CMDIE
1 DBSYIE
0 BTIE
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Section 19 Multimedia Card Interface (MCIF)
Description
FIFO Empty Interrupt Enable
When this bit is set to 1 while the INTRQ0E bit
is 1, the data FIFO empty interrupt request is
enabled.
FIFO Full Interrupt Enable
When this bit is set to 1 while the INTRQ0E bit
is 1, the receive data FIFO full interrupt request
is enabled.
Data Response Interrupt Enable
When this bit is set to 1 in SPI mode with the
INTRQ1E bit as 1, the data response interrupt
request is enabled.
Data Transfer End Interrupt Enable
When this bit is set to 1 while the INTRQ1E bit
is 1, the data transfer end interrupt request is
enabled.
Command Response End Interrupt Enable
When this bit is set to 1 while the INTRQ1E bit
is 1, the command response end interrupt
request is enabled.
Command Transmission End Interrupt Enable
When this bit is set to 1 while the INTRQ1E bit
is 1, the command transmission end interrupt
request is enabled.
Data Busy End Interrupt Enable
When this bit is set to 1 while the INTRQ1E bit
is 1, the data busy end interrupt request is
enabled.
Multiblock Transfer End Interrupt Enable
When this bit is set to 1 with the INTRQ1E bit
as 1, the multiblock transfer end interrupt
request is enabled.
Rev. 3.00 Jan 25, 2006 page 647 of 872
REJ09B0286-0300