Valid Strobes; Basic Operation Timing; Table 6.10 Data Buses Used And Valid Strobes - Renesas H8S/2158 User Manual

Section 6 Bus Controller
6.7.2

Valid Strobes

Table 6.10 shows the data buses used and valid strobes.

Table 6.10 Data Buses Used and Valid Strobes

Access Read/
Size Write Address
Byte Read Even
Odd
Write Even
Odd
Word Read —
Write —
Notes: Undefined: Undefined data is output.
Invalid: Input state with the input value ignored.
6.7.3

Basic Operation Timing

The memory card interface is basically specified as having 3 access states. Figure 6.17 shows the
access timing in memory card mode. The strobe signal waveform for the rising edge and falling
edge at address output can be moved one state by setting the OWEAC and OWENC bits in BCR,
respectively. In this case, wait states must be inserted. For 2-state access, clear both the OWEAC
and OWENC bits to 0. In addition, note that in 3-state access, set the OWEAC and OWENC bits
to B'01 or B'10. Figure 6.18 shows the access timing in memory card mode when the OWEAC and
OWENC bits are set to 1 simultaneously.
Rev. 3.00 Jan 25, 2006 page 138 of 872
REJ09B0286-0300
C C C C PCS1 PCS1 CPCS2 CPCS2
PCS1 PCS1 CPCS2 CPCS2
Valid
Pin Pin Strobe
L H CPOE
L H
L H CPWE
L H
L L CPOE
L L CPWE
Upper Data Bus Lower Data
(D15 to D8) Bus (D7 to D0)
Invalid Valid
(even data)
Invalid Valid
(odd data)
Undefined Valid
(even data)
Undefined Valid
(even data)
Valid (odd data) Valid
(even data)
Valid (odd data) Valid
(even data)