Table 5.9 Interrupt Source Selection And Clearing Control - Renesas H8S/2158 User Manual

Section 5 Interrupt Controller
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
Table 5.9 summarizes interrupt source selection and interrupt source clearance control according
to the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB
in the DTC.
Table 5.9 Interrupt Source Selection and Clearing Control
Settings
DTC
DTCE
0
1
Legend:
∆: The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
: The relevant interrupt is used. The interrupt source is not cleared.
×: The relevant bit cannot be used.
*: Don't care
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DISEL
*
0
1
Interrupt Source Selection/Clearing Control
DTC
×
∆
CPU
∆
×
∆