Operation; Single Mode - Renesas H8S/2158 User Manual

The A/D converter repeats A/D conversion of input channel 0 according to the settings of ADCSR
and ADCR. Input channel 0 is connected to CIN7 to CIN0. The KBCH2 to KBCH0 bits in
KBCOMP select one channel among CIN7 to CIN0. The KBCH2 to KBCH0 bits are
automatically incremented by the DTC when the SCANE bit is set to 1.
When one A/D conversion is completed, the ADF flag in ADSCR is set to 1, and an ADI interrupt
request is generated. The DTC is activated according to the ADI interrupt request, and data is
transferred from ADDRA to on-chip RAM. At this time, the lower four bits of DAR are ignored,
and replaced with the previous contents of bits KBCH2 to KBCH0
22.5

Operation

The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When changing the operating mode or analog input
channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D
conversion. The ADST bit can be set at the same time as the operating mode or analog input
channel is changed.
22.5.1

Single Mode

In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion on the specified channel is started when the ADST bit in ADCSR is set to 1,
by software or an external trigger input.
2. When A/D conversion is completed, the result is transferred to the A/D data register
corresponding to the channel.
3. On completion of A/D conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to
1 at this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion. When conversion ends, the ADST bit is
automatically cleared to 0, and the A/D converter enters wait state.
Section 22 A/D Converter
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Rev. 3.00 Jan 25, 2006 page 705 of 872
REJ09B0286-0300