Waveform Forming Circuit; Clock Select Circuit; Pll Circuit; Figure 26.7 Subclock Input Timing - Renesas H8S/2158 User Manual

EXCL
26.6

Waveform Forming Circuit

To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided φ
clock. The sampling frequency is set by the NESEL bit in LPWRCR.
The subclock is not sampled in subactive mode, subsleep mode, or watch mode.
26.7

Clock Select Circuit

The clock select circuit selects the system clock that is used in this LSI.
Either a clock generated by an oscillator to which the EXTAL and XTAL pins are input or a 24-
MHz clock generated by multiplication in the PLL circuit is selected as a system clock when
returning from high-speed mode, medium-speed mode, sleep mode, or software standby mode. A
clock generated by an oscillator to which the EXTAL and XTAL pins are input is selected as a
system clock when returning from the reset state or hardware standby mode.
A subclock input from the EXCL pin is selected as a system clock in subactive mode, subsleep
mode, or watch mode. At this time, modules such as the CPU, TMR_0, TMR_1, WDT_0,
WDT_1, ports, and interrupt controller and their functions operate depending on the φSUB. The
count clock and sampling clock for each timer are divided φSUB clocks.
26.8

PLL Circuit

This LSI incorporates a PLL circuit which generates a 48-MHz clock (φ48) or a 24-MHz clock
(φ24) obtained by dividing the 48-MHz clock by two as the USB operating clock. The clock
source is the clock input from the USEXCL pin or the clock generated by an oscillator to which
the EXTAL and XTAL pins are input. The PLL input clock must be 8, 12, 16, 20, or 24 MHz. The
48-MHz clock input to the USEXCL pin can be directly used as the USB operating clock instead
t
EXCLH
t
EXCLr

Figure 26.7 Subclock Input Timing

Section 26 Clock Pulse Generator
t
EXCLL
V × 0.5
CC
t
EXCLf
Rev. 3.00 Jan 25, 2006 page 767 of 872
REJ09B0286-0300