Operation Control Register (Opcr) - Renesas H8S/2158 User Manual

19.3.9

Operation Control Register (OPCR)

OPCR controls command operation abort, and suspends or continues data transfer.
Bit Bit Name
7 CMDOFF
6 —
5 RD_CONTI
Initial Value R/W
0 W
0 R/(W)
0 W
Section 19 Multimedia Card Interface (MCIF)
Description
Command Off
Always read as 0. Aborts all command
operations (MCIF command sequence) when 1
is written after a command is transmitted.
Write enable period: From command
transmission completion to command
sequence end
0: Operation is not affected.
1: Command sequence is forcibly aborted.
Byte transfer during transfer is also
suspended.
After command sequence abort, the transfer
clock output resumes if the transfer clock has
been halted during the command sequence.
Reserved
The initial value should not be changed.
Read Continue
Read as 1 until resuming read when 1 is
written. Otherwise, read as 0. Resumes
transfer clock output and read data reception
when the transfer clock is halted according to
FIFO full or termination of block reading in
multiblock read.
Write enable period: While MCCLK for read
data reception is halted
0: Operation is not affected.
1: Resumes MCCLK output and read data
reception.
Rev. 3.00 Jan 25, 2006 page 641 of 872
REJ09B0286-0300