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Figure 27.4 shows an example of hardware standby mode timing.
Oscillator
RES
STBY
27.7
Watch Mode
The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed
mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR
cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1.
In watch mode, the CPU is stopped and peripheral modules other than WDT_1 are also stopped.
The contents of the CPU's internal registers, several on-chip peripheral module registers, and on-
chip RAM data are retained and the I/O ports retain their values before transition as long as the
prescribed voltage is supplied.
Watch mode is exited by an interrupt (WOVI1, NMI, IRQ15 to IRQ0, KIN9 to KIN0, or WUE15
to WUE8), RES pin input, or STBY pin input.
When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or
medium-speed mode when the LSON bit in LPWRCR cleared to 0 or to subactive mode when the
LSON bit is set to 1. When a transition is made to high-speed mode, a stable clock is supplied to
the entire LSI and interrupt exception handling starts after the time set in the STS2 to STS0 bits in
SBYCR has elapsed.
In the case of an IRQ15 to IRQ0 interrupt, watch mode is not exited if the corresponding enable
bit has been cleared to 0 or the interrupt is masked by the CPU. In the case of a KIN9 to KIN0 or
WUE15 to WUE8 interrupt, watch mode is not exited if input is disabled or the interrupt is
Figure 27.4 Hardware Standby Mode Timing
Section 27 Power-Down Modes
Oscillation
stabilization
time
Rev. 3.00 Jan 25, 2006 page 785 of 872
Reset
exception
handling
REJ09B0286-0300
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