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Section 27 Power-Down Modes
states of on-chip peripheral modules other than the SCI, PWM, and PWMX, are retained as long
as the prescribed voltage is supplied.
Software standby mode is cleared by an external interrupt (NMI, IRQ15 to IRQ0, KIN9 to KIN0,
or WUE15 to WUE8), the RES pin input, or STBY pin input.
When an external interrupt request signal is input, system clock oscillation starts, and after the
elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and
interrupt exception handling is started. When exiting software standby mode with an IRQ15 to
IRQ0 interrupt, set the corresponding enable bit to 1. When exiting software standby mode with a
KIN9 to KIN0 or WUE15 to WUE8 interrupt, enable the input. In these cases, ensure that no
interrupt with a higher priority than interrupts IRQ15 to IRQ0 is generated. In the case of an
IRQ15 to IRQ0 interrupt, software standby mode is not exited if the corresponding enable bit is
cleared to 0 or if the interrupt has been masked by the CPU. In the case of a KIN9 to KIN0 or
WUE15 to WUE8 interrupt, software standby mode is not exited if input is disabled or if the
interrupt has been masked by the CPU.
When the RES pin is driven low, system clock oscillation is started. At the same time as system
clock oscillation starts, the system clock is supplied to the entire LSI. Note that the RES pin must
be held low until clock oscillation stabilizes. When the RES pin goes high after clock oscillation
stabilizes, the CPU begins reset exception handling.
When the STBY pin is driven low, software standby mode is cancelled and a transition is made to
hardware standby mode.
Figure 27.3 shows an example in which a transition is made to software standby mode at the
falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge of the NMI pin.
Rev. 3.00 Jan 25, 2006 page 783 of 872
REJ09B0286-0300
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