Figure 16.28 Receive Data Sampling Timing In Smart Card Interface Mode (When Clock Frequency Is 372 Times The Bit Rate) - Renesas H8S/2158 User Manual

Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in
figure 16.28. The reception margin here is determined by the following formula.
M = (0.5 –
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock rate deviation
Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is
determined by the formula below.
M = (0.5 – 1/2 × 372)
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 16.28 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock
Rev. 3.00 Jan 25, 2006 page 448 of 872
REJ09B0286-0300
D – 0.5
1
) – (L – 0.5) F –
2N
× 100[%] = 49.866%
372 clock cycles
186 clock
cycles
0 185 371
Start bit
Frequency Is 372 Times the Bit Rate)
(1 + F) × 100 [%]
N
185
0
D0
..... Formula (1)
371 0
D1