Figure 18.79 Tcnt_2 Write And Overflow/Underflow Conflict With Cascade Connection - Renesas HD6417641 Hardware Manual

Pφ
Address
Write signal
TCNT_2
TGR2A_2 to
TGR2B_2
Ch2 compare-
match signal A/B
TCNT_1 input
clock
TCNT_1
TGRA_1
Ch1 compare-
match signal A
TGRB_1
Ch1 input capture
signal B
TCNT_0
TGRA_0 to
TGRD_0
Ch0 input capture
signal A to D

Figure 18.79 TCNT_2 Write and Overflow/Underflow Conflict with Cascade Connection

Section 18 Multi-Function Timer Pulse Unit (MTU)
TCNT write cycle
T1
TCNT_2 address
H'FFFE H'FFFF
TCNT_2 write data
H'FFFF
M
M
N
P
Q
T2
N N + 1
Disabled
M
P
Rev. 4.00 Sep. 14, 2005 Page 635 of 982
REJ09B0023-0400