Tcnt External Reset Timing; Timing Of Overflow Flag (Ovf) Setting; Figure 10.10 Timing Of Counter Clear By External Reset Input; Figure 10.11 Timing Of Ovf Flag Setting - Renesas H8S/2111B Hardware Manual

10.5.5

TCNT External Reset Timing

TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
10.10 shows the timing of clearing the counter by an external reset input.
φ
External reset
input pin
Clear signal
TCNT

Figure 10.10 Timing of Counter Clear by External Reset Input

10.5.6

Timing of Overflow Flag (OVF) Setting

The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure
10.11 shows the timing of OVF flag setting.
φ
TCNT
Overflow signal
OVF
N – 1
H'FF

Figure 10.11 Timing of OVF Flag Setting

N H'00
H'00
Rev. 1.00, 05/04, page 209 of 544