Timer Control/Status Registers 0 To 3 (Tcsr0 To Tcsr3) - Renesas H8S/2633 Series Hardware Manual

13.2.5

Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3)

TCSR0
Bit : 7
CMFB
Initial value :
0
R/W : R/(W)*
TCSR1, TCSR3
Bit : 7
CMFB
Initial value : 0
R/W : R/(W)*
TCSR2
Bit : 7
CMFB
Initial value : 0
R/W : R/(W)*
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
TCSR0 to TCSR3 are 8-bit registers that display compare match and timer overflow statuses, and
control compare match output.
TCSR0 and TCSR2 are initialized to H'00, and TCSR1 and TCSR3 to H'10, by a reset and in
hardware standby mode.
6 5
CMFA OVF ADTE
0 0
R/(W)* R/(W)* R/W
6 5
CMFA OVF
0 0
R/(W)* R/(W)*
6 5
CMFA OVF
0 0
R/(W)* R/(W)* R/W
4 3 2
OS3 OS2
0 0 0
R/W R/W
4 3 2
— OS3
OS2
1 0 0
— R/W R/W
4 3 2
— OS3 OS2
0 0 0
R/W R/W
1 0
OS1 OS0
0 0
R/W R/W
1 0
OS0
OS1
0 0
R/W R/W
1 0
OS1 OS0
0
0
R/W R/W
637