Timer Synchro Register (Tsyr) - Renesas H8S/2633 Series Hardware Manual

11.2.9

Timer Synchro Register (TSYR)

Bit : 7
—
Initial value : 0
R/W : —
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channels 0 to 5 TCNT counters. A channel performs synchronous operation
when the corresponding bit in TSYR is set to 1.
TSYR is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 and 6—Reserved: Should always be written with 0.
Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, synchronous presetting of multiple channels*
synchronous clearing through counter clearing on another channel*
Bit n
SYNCn Description
0 TCNTn operates independently (TCNT presetting/clearing is unrelated to
other channels)
1 TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing is possible
Notes: *1 To set synchronous operation, the SYNC bits for at least two channels must be set to 1.
*2 To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source
must also be set by means of bits CCLR2 to CCLR0 in TCR.
550
6 5 4
— SYNC5 SYNC4
0 0 0
— R/W R/W
3 2
SYNC3 SYNC2 SYNC1
0 0
R/W R/W
2
are possible.
1 0
SYNC0
0 0
R/W R/W
1
, and
(Initial value)
n = 5 to 0