Timer Synchro Register (Tsyr) - Renesas H8S/2437 Hardware Manual

Renesas 16-bit single-chip microcomputer h8s family / h8s / 2600 series
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12.3.9

Timer Synchro Register (TSYR)

TSYR selects independent operation or synchronous operation for TCNT in channels 0 to 2.
Synchronous operation is performed in the channel when the corresponding bit in TSYR is set to
1.
Bit
Bit Name Initial Value
7 to 3 
All 0
2
SYNC2
0
1
SYNC1
0
0
SYNC0
0
Rev. 1.00, 09/03, page 324 of 704
R/W
Description
Reserved
The write value should always be 0.
R/W
Timer Synchro 2 to 0
R/W
Select whether operation is independent of or
synchronized with other channels.
R/W
When synchronous operation is selected, synchronous
presetting of multiple channels and synchronous clearing
due to counter clearing on another channel are possible.
To set synchronous operation, the SYNC bits for at least
two channels must be set to 1. To set synchronous
clearing, in addition to the SYNC bit, the TCNT clearing
source must also be set by means of bits CCLR2 to
CCLR0 in TCR.
0: TCNTn operates independently
(TCNT presetting/clearing is unrelated to other
channels)
1: TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing is
possible
(n = 2 to 0)

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