Timer Synchronous Register (Tsyr) - Renesas H8SX/1520 Series Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.9

Timer Synchronous Register (TSYR)

TSYR selects independent operation or synchronous operation for the TCNT counters of channels
0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit
Bit Name
Initial Value
R/W
Bit Bit Name

7, 6
5 SYNC5
4 SYNC4
3 SYNC3
2 SYNC2
1 SYNC1
0 SYNC0
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7 6
— — SYNC5
0 0
R/W R/W R/W
Initial
value R/W
All 0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
5 4 3
SYNC4 SYNC3
0 0 0
R/W R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Timer Synchronization 5 to 0
These bits select whether operation is independent of or
synchronized with other channels.
When synchronous operation is selected, synchronous
presetting of multiple channels, and synchronous clearing
through counter clearing on another channel are possible.
To set synchronous operation, the SYNC bits for at least
two channels must be set to 1. To set synchronous
clearing, in addition to the SYNC bit, the TCNT clearing
source must also be set by means of bits CCLR2 to
CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operate independently (TCNT
presetting/clearing is unrelated to other channels)
1: TCNT_5 to TCNT_0 perform synchronous operation
(TCNT synchronous presetting/synchronous clearing
is possible)
2 1
SYNC2 SYNC1 SYNC0
0 0
R/W R/W
0
0
R/W