Timer Synchronous Register (Tsyr) - Renesas H8S/2368 Series Hardware Manual

10.3.9

Timer Synchronous Register (TSYR)

TSYR selects independent operation or synchronous operation for the TCNT counters of channels
0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit Bit Name Initial value
– –
7
– –
6
5 SYNC5 0
4 SYNC4 0
3 SYNC3 0
2 SYNC2 0
1 SYNC1 0
0 SYNC0 0
Rev. 2.00, 05/03, page 410 of 820
R/W Description
R/W Reserved
R/W
The write value should always be 0.
R/W Timer Synchronization 5 to 0
R/W
These bits select whether operation is independent of
R/W
or synchronized with other channels.
R/W
When synchronous operation is selected,
R/W
synchronous presetting of multiple channels, and
R/W
synchronous clearing through counter clearing on
another channel are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit, the
TCNT clearing source must also be set by means of
bits CCLR2 to CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operates independently
(TCNT presetting /clearing is unrelated to
other channels)
1: TCNT_5 to TCNT_0 performs synchronous
operation (TCNT synchronous presetting/
synchronous clearing is possible)