Timer Synchro Register (Tsyr) - Renesas H8S Series Hardware Manual

Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.9

Timer Synchro Register (TSYR)

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channel 0 to 5 TCNT counters. A channel performs synchronous operation when
the corresponding bit in TSYR is set to 1.
Bit Bit Name Initial value
7, 6 — All 0
5 SYNC5 0
4 SYNC4 0
3 SYNC3 0
2 SYNC2 0
1 SYNC1 0
0 SYNC0 0
Rev. 6.00 Mar 15, 2006 page 196 of 570
REJ09B0211-0600
R/W Description
R/W Reserved
Only 0 should be written to these bits.
R/W Timer Synchro 0 to 5
R/W
These bits are used to select whether operation is
R/W
independent of or synchronized with other channels.
R/W
When synchronous operation is selected, the TCNT
R/W
synchronous presetting of multiple channels, and
R/W
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit,
the TCNT clearing source must also be set by means
of bits CCLR0 to CCLR2 in TCR.
0: TCNT_0 to TCNT_5 operates independently
(TCNT presetting /clearing is unrelated to
other channels)
1: TCNT_0 to TCNT_5 performs synchronous
operation
TCNT synchronous presetting/synchronous clearing
is possible