Bus Control Register L (Bcrl) - Renesas H8S/2319 series Hardware Manual

Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0 Description
0 Max. 4 words in burst access
1 Max. 8 words in burst access
Bits 2 to 0—Reserved: Only 0 should be written to these bits.
6.2.5

Bus Control Register L (BCRL)

Bit : 7
BRLE
Initial value : 0
R/W : R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, selection of the area division unit, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE Description
External bus release is disabled. BREQ, BACK, and BREQO pins can be used as I/O
0
ports
1 External bus release is enabled
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access.
Bit 6
BREQOE Description
BREQO output disabled. BREQO pin can be used as I/O port
0
BREQO output enabled
1
Rev. 5.00, 12/03, page 150 of 1088
6 5
BREQOE EAE
0 1
R/W R/W
4 3
— —
1 1
R/W R/W R/W
(Initial value)
2 1
— — WAITE
1 0
R/W R/W
(Initial value)
(Initial value)
0
0