ST STM32L4+ Series Reference Manual page 1414

General-purpose timers (TIM15/TIM16/TIM17)
39.4.22 Timer synchronization (TIM15)
The TIMx timers are linked together internally for timer synchronization or chaining. Refer to
Section 38.3.19: Timer synchronization
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from the
master timer.
39.4.23 Debug mode
When the microcontroller enters debug mode (Cortex
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to
RTC, watchdog, bxCAN and I
For safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1), the outputs are
disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state
(OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0) to force
them to Hi-Z.
1414/2301
for details.
Section 57.16.2: Debug support for timers,
2
C.
RM0432 Rev 6
®
-M4 core halted), the TIMx counter
RM0432