ST STM32L4+ Series Reference Manual page 1422

General-purpose timers (TIM15/TIM16/TIM17)
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
Bit 1 CC1IF: Capture/Compare 1 interrupt flag
Bit 0 UIF: Update interrupt flag
39.5.6 TIM15 event generation register (TIM15_EGR)
Address offset: 0x14
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
1422/2301
refer to CC1IF description
This flag is set by hardware. It is cleared by software (input capture or output compare
mode) or by reading the TIMx_CCR1 register (input capture mode only).
0: No compare match / No input capture occurred
1: A compare match or an input capture occurred
If channel CC1 is configured as output: this flag is set when the content of the counter
TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of
TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the
counter overflow (in up-counting and up/down-counting modes) or underflow (in down-
counting mode). There are 3 possible options for flag setting in center-aligned mode, refer
to the CMS bits in the TIMx_CR1 register for the full description.
If channel CC1 is configured as input: this bit is set when counter value has been
captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge
sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow regarding the repetition counter value (update if repetition counter = 0) and if
the UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to
control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
12 11 10 9
Res. Res. Res.
DMA transfer can occur if enabled.
enabled
8 7 6
Res. BG TG COMG
w w
RM0432 Rev 6
Section 39.5.3: TIM15 slave mode
5 4 3 2
Res. Res. CC2G
rw w
RM0432
1 0
CC1G UG
w w