Cascaded Operation - Renesas H8S/2633 Series Hardware Manual

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Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit

This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow

of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR.

Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.

Table 11-6 shows the register combinations used in cascaded operation.

Note: When phase counting mode is set for channels 1 or 4, the counter clock setting is invalid

and the counter operates independently in phase counting mode.

Table 11-6 Cascaded Combinations

Channels 1 and 2

Channels 4 and 5

Example of Cascaded Operation Setting Procedure: Figure 11-21 shows an example of the

setting procedure for cascaded operation.

Cascaded operation

Set cascading

Figure 11-21 Cascaded Operation Setting Procedure

Upper 16 Bits

[1] Set bits TPSC2 to TPSC0 in the channel 1

(channel 4) TCR to B'111 to select TCNT2

(TCNT5) overflow/underflow counting.

[2] Set the CST bit in TSTR for the upper and lower

channel to 1 to start the count operation.

Lower 16 Bits