Cascaded Operation; Figure 18.17 Example Of Buffer Operation (2); Table 18.30 Cascaded Combinations - Renesas HD6417641 Hardware Manual

Section 18 Multi-Function Timer Pulse Unit (MTU)
TCNT value
H'0F07
H'09FB
H'0532
H'0000
TIOCA
TGRA
TGRC
18.4.4

Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 18.30 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
and the counters operates independently in phase counting mode.

Table 18.30 Cascaded Combinations

Combination
Channels 1 and 2
Rev. 4.00 Sep. 14, 2005 Page 574 of 982
REJ09B0023-0400
H'0532

Figure 18.17 Example of Buffer Operation (2)

Upper 16 Bits
TCNT_1
H'0F07
H'09FB
H'0532 H'0F07
Lower 16 Bits
TCNT_2
Time