Cascaded Operation; Figure 10.17 Cascaded Operation Setting Procedure; Table 10.29 Cascaded Combinations - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit

This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow

of TCNT_2 (TCNT_5) as set in bits TPSC0 to TPSC2 in TCR.

Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.

Table 10.29 shows the register combinations used in cascaded operation.

Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid

and the counters operates independently in phase counting mode.

Channels 1 and 2

Channels 4 and 5

Example of Cascaded Operation Setting Procedure: Figure 10.17 shows an example of the

setting procedure for cascaded operation.

Cascaded operation

Set cascading

Upper 16 Bits

Section 10 16-Bit Timer Pulse Unit (TPU)

Lower 16 Bits

Set bits TPSC2 to TPSC0 in the channel 1

(channel 4) TCR to B'1111 to select TCNT_2

(TCNT_5) overflow/underflow counting.

Set the CST bit in TSTR for the upper and lower

channel to 1 to start the count operation.

Rev. 6.00 Mar 15, 2006 page 209 of 570

REJ09B0211-0600