Cascaded Operation; Figure 9.18 Example Of Cascaded Operation Setting Procedure; Table 9.32 Cascaded Combinations - Renesas H8SX/1520 Series Hardware Manual

9.4.4

Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of
TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 9.32 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
and the counter operates independently in phase counting mode.

Table 9.32 Cascaded Combinations

Combination
Channels 1 and 2
Channels 4 and 5
(1)
Example of Cascaded Operation Setting Procedure
Figure 9.18 shows an example of the setting procedure for cascaded operation.
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Upper 16 Bits
TCNT_1
TCNT_4
Cascaded operation
Set cascading
Start count
<Cascaded operation>

Figure 9.18 Example of Cascaded Operation Setting Procedure

Section 9 16-Bit Timer Pulse Unit (TPU)
Lower 16 Bits
TCNT_2
TCNT_5
[1] Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
Set the CST bit in TSTR for the upper and lower
[2]
[1]
channels to 1 to start the count operation.
[2]
Rev. 3.00 Mar. 14, 2006 Page 311 of 804
REJ09B0104-0300