Cascaded Operation - Renesas H8SX/1650 Hardware Manual

TCNT value
H'0F07
H'09FB
H'0532
H'0000
TIOCA
TGRA
TGRC
9.4.4

Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of
TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 9.30 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
and the counter operates independently in phase counting mode.
Table 9.30 Cascaded Combinations
Combination
Channels 1 and 2
Channels 4 and 5
H'0532
Figure 9.16 Example of Buffer Operation (2)
Upper 16 Bits
TCNT_1
TCNT_4
Section 9 16-Bit Timer Pulse Unit (TPU)
H'0F07 H'09FB
H'0532 H'0F07
Lower 16 Bits
TCNT_2
TCNT_5
Rev.2.00 Jun. 28, 2007 Page 357 of 666
Time
REJ09B0311-0200