Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1572

ADSP-SC58x USB Register Descriptions
Table 27-49: USB_EP[n]_TXCSR_H Register Fields (Continued)
Bit No.
(Access)
7 NAKTOINCMP
(R/W0C)
6 CLRDATATGL
(R/W)
5 RXSTALL
(R/W0C)
4 SETUPPKT
(R/W)
3 FLUSHFIFO
(R/W)
27–160
Bit Name
NAK Timeout Incomplete.
The USB_EP[n]_TXCSR_H.NAKTOINCMP bit indicates (for bulk endpoints in
host mode) when the transmit endpoint is halted following the receipt of NAK re-
sponses for longer than the time set in the
processor should clear this bit, allowing the endpoint to continue. For products sup-
porting high-speed operation, for high-bandwidth isochronous endpoints in host
mode, this bit indicates when no response is received from the device to which the
packet is being sent.
Clear Endpoint Data Toggle.
The USB_EP[n]_TXCSR_H.CLRDATATGL bit is set (in host mode) by the pro-
cessor to reset the endpoint data toggle to 0.
Rx STALL.
The USB_EP[n]_TXCSR_H.RXSTALL bit indicates (in host mode) when a
STALL handshake is received. The processor core should clear this bit.
Setup Packet.
The USB_EP[n]_TXCSR_H.SETUPPKT bit directs (in host mode) the USB con-
troller to send a SETUP token instead of an OUT token for the transaction. This bit is
set at the same time as the USB_EP[n]_TXCSR_H.TXPKTRDY bit is set.
Flush Endpoint FIFO.
The USB_EP[n]_TXCSR_H.FLUSHFIFO bit directs (in host mode) the USB
controller to flush data from the endpoint FIFO and clear the
USB_EP[n]_TXCSR_H.TXPKTRDY bit. The
USB_EP[n]_TXCSR_H.FLUSHFIFO bit should only be set if the
USB_EP[n]_TXCSR_H.TXPKTRDY bit is set.
Note that setting this bit at other times may cause data corruption.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
USB_EP[n]_TXINTERVAL
0 No Status
1 NAK Timeout Over Maximum
0 No Action
1 Reset EP Data Toggle to 0
0 No Status
1 Stall Received from Device
0 No Request
1 Send SETUP Token
0 No Flush
1 Flush Endpoint FIFO
register. The