Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1617

Low-Speed EOF 1 Register
The register defines the minimum time gap allowed between the start of the last transaction and
USB_LS_EOF1
the end of frame for low-speed transactions.
Figure 27-99: USB_LS_EOF1 Register Diagram
Table 27-75: USB_LS_EOF1 Register Fields
Bit No.
(Access)
7:0 VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
VALUE (R/W)
Low-Speed EOF 1 Value
Bit Name
Low-Speed EOF 1 Value.
The USB_LS_EOF1.VALUE bits set the time before end of frame to stop beginning
new transactions (in units of 1.067us) for low-speed transactions. The default setting
corresponds to 121.6us.
7 6 5 4 3 2 1 0
0 1 1 1 0 0 1 0
Description/Enumeration
ADSP-SC58x USB Register Descriptions
27–205