Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1634

ADSP-SC58x USB Register Descriptions
Software Reset Register
The
USB_SOFT_RST
USB controller PHY operates in the controller's XCLK domain, and the USB controller interface to the processor
core operates in the controller's CLK domain. Note that for correct operation, both of the reset control bits
(USB_SOFT_RST.RST and USB_SOFT_RST.RSTX) should always be asserted simultaneously.
Figure 27-113: USB_SOFT_RST Register Diagram
Table 27-89: USB_SOFT_RST Register Fields
Bit No.
(Access)
1 RSTX
(R/W)
0 RST
(R/W)
27–222
register provides reset controls for the USB controller CLK domain and XCLK domain. The
7 6
0 0
RSTX (R/W)
Reset USB XCLK Domain
Bit Name
Reset USB XCLK Domain.
The USB_SOFT_RST.RSTX bit resets logic in the USB XCLK domain. This bit is
self-clearing. Note that this bit should always be asserted simultaneously with the
USB_SOFT_RST.RST bit.
Reset USB CLK Domain.
The USB_SOFT_RST.RST bit resets logic in the USB CLK domain. This bit is self-
clearing. Note that this bit should always be asserted simultaneously with the
USB_SOFT_RST.RSTX bit.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
5 4 3 2 1 0
0 0 0 0 0 0
RST (R/W)
Reset USB CLK Domain
Description/Enumeration
0 No Reset
1 Reset USB XCLK Domain
0 No Reset
1 Reset USB CLK Domain