Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1635

Sharc+ processor
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Testmode Register
The
USB_TESTMODE
ler into one of the test modes for high-speed operation. For more information about these modes, see the USB 2.0
specification.
Note that the
USB_TESTMODE
tion bits may be set at a time.
Figure 27-114: USB_TESTMODE Register Diagram
Table 27-90: USB_TESTMODE Register Fields
Bit No.
(Access)
6
FIFOACCESS
(R/W)
3
TESTPACKET
(R/W)
2
TESTK
(R/W)
1
TESTJ
(R/W)
0
TESTSE0NAK
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register places the USB controller into the test mode state and can also put the USB control-
register is not used in normal operation. Only one of the test mode (bits 0-6) selec-
7
0
FIFOACCESS (R/W)
FIFO Access
TESTPACKET (R/W)
Test_Packet Mode
TESTK (R/W)
Test_K Mode
Bit Name
FIFO Access.
The
USB_TESTMODE
point 0 Tx FIFO to the endpoint 0 Rx FIFO. The bit is cleared automatically.
Test_Packet Mode.
The USB_TESTMODE.TESTPACKET bit selects Test_Packet test mode, which ap-
plies only when the USB controller is in high-speed mode. In this mode, the USB
controller repetitively transmits on the bus a 53-byte test packet, whose form is defined
in the USB 2.0 Specification, Section 7.1.20. Note that the test packet has a fixed for-
mat and must be loaded into the endpoint 0 FIFO before this test mode is entered.
Test_K Mode.
The USB_TESTMODE.TESTK bit selects Test_K test mode. In this mode, the USB
controller transmits a continuous K on the bus.
Test_J Mode.
The USB_TESTMODE.TESTJ bit selects Test_J test mode. In this mode, the USB
controller transmits a continuous J on the bus.
Test SE0 NAK.
The USB_TESTMODE.TESTSE0NAK bit selects Test_SE0_NAK test mode, which
applies only when the USB controller is in high-speed mode. In this mode, the USB
controller remains in high-speed mode, but responds to any valid IN token with a
NAK.
6
5
4
3
2
1
0
0
0
0
0
0
0
0
TESTSE0NAK (R/W)
Test SE0 NAK
TESTJ (R/W)
Test_J Mode
Description/Enumeration
bit directs the USB controller to transfer the packet in the end-
ADSP-SC58x USB Register Descriptions
27–223

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