RAM Information Register
The
register provides information about the width of the USB controller RAM.
USB_RAMINFO
Figure 27-109: USB_RAMINFO Register Diagram
Table 27-85: USB_RAMINFO Register Fields
Bit No.
(Access)
7:4
DMACHANS
(R/NW)
3:0
RAMBITS
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7
1
DMACHANS (R)
DMA Channels
Bit Name
DMA Channels.
The USB_RAMINFO.DMACHANS bits indicate the number of DMA channels.
RAM Address Bits.
The USB_RAMINFO.RAMBITS bits indicate the number of RAM address bits. The
USB controller FIFO RAM is 32-bits wide. The number of bytes in the FIFO RAM
may be calculated from the formula:
RAM_bytes = 2
6
5
4
3
2
1
0
0
0
0
1
1
0
0
RAMBITS (R)
RAM Address Bits
Description/Enumeration
(RAM_Bits+2)
ADSP-SC58x USB Register Descriptions
27–217
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