Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1567

EPn Receive Maximum Packet Length Register
The
USB_EP[n]_RXMAXP
lected receive endpoint in a single frame.
Note that a value greater than the maximum allowed of 1023 for full-speed USB operation produces unpredictable
results. Also, note that the total amount of data represented by the value written to this register must not exceed the
receive FIFO size, and should not exceed half the FIFO size if double-buffering is required.
MULTM1 (R/W)
Multi-Packets per Micro-frame
Figure 27-71: USB_EP[n]_RXMAXP Register Diagram
Table 27-47: USB_EP[n]_RXMAXP Register Fields
Bit No.
(Access)
12:11 MULTM1
(R/W)
10:0 MAXPAY
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register defines the maximum amount of data that can be transferred through the se-
15 14 13 12 11 10
0 0 0 0 0
Bit Name
Multi-Packets per Micro-frame.
The USB_EP[n]_RXMAXP.MULTM1 bits select the number of high-speed, high-
bandwidth isochronous or interrupt packets that may be transferred in a micro-frame.
The valid number of packets per micro-frame is 1-3 which corresponds to settings 0-2.
If this field is not zero, the USB controller combines multiple packets received within a
micro-frame into a single packet in the FIFO.
Maximum Payload.
The USB_EP[n]_RXMAXP.MAXPAY bits select the maximum number of bytes that
may be transferred per transaction. This field can be up to 1024, but is subject to con-
straints by the USB specification based on endpoint mode and speed. This field should
not exceed the FIFO size for the endpoint, or half the FIFO size if double buffering is
used. This value should match the wMaxPacketSize field of the standard endpoint de-
scriptor (USB 2.0 spec, section 9). The USB_EP[n]_RXMAXP.MAXPAY bits must
be set to an even number of bytes for proper interrupt generation in DMA mode 1.
9 8 7 6 5 4 3 2
0 0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x USB Register Descriptions
1 0
0 0
MAXPAY (R/W)
Maximum Payload
27–155