Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1625

PLL and Oscillator Control Register
The register provides access to PLL and oscillator-related control features.
USB_PLL_OSC
PLLSTABLE (R)
PLL Stable
PLLMSEL (R/W)
PLL Multiplier Select
Figure 27-107: USB_PLL_OSC Register Diagram
Table 27-83: USB_PLL_OSC Register Fields
Bit No.
(Access)
14 PLLSTABLE
(R/NW)
7 PLLMSEL
(R/W)
6:1 PLLM
(R/W)
0 DIVCLKIN
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15 14 13 12 11 10
0 0 0 0 0 0
Bit Name
PLL Stable.
The USB_PLL_OSC.PLLSTABLE status bit indicates that the oscillator and PLL
clock are stable.
PLL Multiplier Select.
The USB_PLL_OSC.PLLMSEL bit directs the PLL to use the PLL multiplier value
stored in the USB_PLL_OSC.PLLM bits.
PLL Multiplier Value.
The USB_PLL_OSC.PLLM bit field contains the PLL multiplier. This field should
be set such that CLKIN * USB_PLL_OSC.PLLM value = 480MHz.
Divide CLKIN.
The USB_PLL_OSC.DIVCLKIN bit enables a divide CLKIN by 2 function for the
PLL.
9 8 7 6 5 4 3 2
0 0 0 0 0 1 0 1
Description/Enumeration
ADSP-SC58x USB Register Descriptions
1 0
0 0
DIVCLKIN (R/W)
Divide CLKIN
PLLM (R/W)
PLL Multiplier Value
27–213