Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1570

ADSP-SC58x USB Register Descriptions
EPn Transmit Configuration and Status (Host) Register
The
USB_EP[n]_TXCSR_H
rently-selected transmit endpoint.
AUTOSET (R/W)
TxPkRdy Autoset Enable
DMAREQEN (R/W)
DMA Request Enable Tx EP
FRCDATATGL (R/W)
Force Data Toggle
DMAREQMODE (R/W)
DMA Mode Select
DATGLEN (R/W)
Data Toggle Write Enable
DATGL (R/W)
Data Toggle
NAKTOINCMP (R/W0C)
NAK Timeout Incomplete
Figure 27-73: USB_EP[n]_TXCSR_H Register Diagram
Table 27-49: USB_EP[n]_TXCSR_H Register Fields
Bit No.
(Access)
15 AUTOSET
(R/W)
12 DMAREQEN
(R/W)
27–158
register provides (in host mode) control and status bits for transfers through the cur-
15 14 13 12 11 10 9
0 0 0 0 0 0 0
Bit Name
TxPkRdy Autoset Enable.
The USB_EP[n]_TXCSR_H.AUTOSET bit enables (in host mode) the automatic
setting of the USB_EP[n]_TXCSR_H.TXPKTRDY bit when the maximum data
packet size (USB_EP[n]_TXMAXP) is loaded into the transmit FIFO. The
USB_EP[n]_TXMAXP
the maximum packet size is loaded, the USB_EP[n]_TXCSR_H.TXPKTRDY bit
needs to be set manually. For products supporting high-speed operation, this
USB_EP[n]_TXCSR_H.AUTOSET bit should not be set for high-bandwidth end-
points (endpoints with
DMA Request Enable Tx EP.
The USB_EP[n]_TXCSR_H.DMAREQEN bit enables (in host mode) DMA re-
quests for this transmit endpoint.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
Description/Enumeration
value must be a word (4-byte) multiple. If a packet less than
USB_EP[n]_TXMAXP
0 Disable Autoset
1 Enable Autoset
0 Disable DMA Request
1 Enable DMA Request
0
0
TXPKTRDY (R/W1S)
Tx Packet Ready
NEFIFO (R)
Not Empty FIFO
TXTOERR (R/W0C)
Tx Timeout Error
FLUSHFIFO (R/W)
Flush Endpoint FIFO
SETUPPKT (R/W)
Setup Packet
RXSTALL (R/W0C)
Rx STALL
CLRDATATGL (R/W)
Clear Endpoint Data Toggle
value greater than 1).