Dtc Transfer Count Register B (Crb); Dtc Enable Registers (Dtcer) - Renesas H8S/2319 series Hardware Manual

7.2.6

DTC Transfer Count Register B (CRB)

Bit : 15
Initial value :
Unde-
fined
R/W : —
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
7.2.7

DTC Enable Registers (DTCER)

Bit : 7
DTCE7
Initial value : 0
R/W : R/W
The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF,
with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or
disable DTC service for the corresponding interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn Description
0 DTC activation by this interrupt is disabled
[Clearing conditions]
•
When the DISEL bit is 1 and the data transfer has ended
•
When the specified number of transfers have ended
1 DTC activation by this interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 7-5, together with the vector numbers
generated by the interrupt controller.
Rev. 5.00, 12/03, page 190 of 1088
14 13 12 11
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined
— — — —
6 5
DTCE6 DTCE5
0 0
R/W R/W
10 9 8 7
Unde- Unde- Unde- Unde-
fined fined fined fined fined
— — — —
4 3
DTCE4 DTCE3
0 0
R/W R/W
6 5 4 3
Unde- Unde- Unde- Unde-
fined fined fined fined
— — — — —
2 1
DTCE2 DTCE1
0 0
R/W R/W
2 1 0
Unde- Unde-
fined fined
— —
0
DTCE0
0
R/W
(Initial value)
(n = 7 to 0)