Dtc Transfer Count Register B (Crb); Dtc Enable Registers (Dtcer) - Renesas H8S/2633 Series Hardware Manual

9.2.6

DTC Transfer Count Register B (CRB)

Bit : 15 14
Initial value : Unde- Unde-
fined fined
— —
R/W :
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
9.2.7

DTC Enable Registers (DTCER)

7
Bit :
DTCE7
0
Initial value :
R/W : R/W
The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to DTCERF
and DTCERI, with bits corresponding to the interrupt sources that can control enabling and
disabling of DTC activation. These bits enable or disable DTC service for the corresponding
interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn Description
0 DTC activation by this interrupt is disabled
[Clearing conditions]
•
When the DISEL bit is 1 and the data transfer has ended
•
When the specified number of transfers have ended
1 DTC activation by this interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 9-4, together with the vector number
generated for each interrupt controller.
336
13 12 11 10
Unde- Unde- Unde- Unde- Unde-
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— — — —
6 5
DTCE6 DTCE5
0 0
R/W R/W
9 8 7 6
Unde- Unde- Unde- Unde-
fined fined fined fined fined
— — — —
4
3
DTCE4 DTCE3 DTCE2
0 0
R/W R/W
5 4 3 2
Unde- Unde- Unde- Unde-
fined fined fined fined
— — — — —
2 1
DTCE1 DTCE0
0 0
R/W R/W R/W
(Initial value)
(n = 7 to 0)
1 0
Unde-
fined
—
0
0