Dtc Enable Registers A To H (Dtcera To Dtcerh) - Renesas H8SX/1650 Hardware Manual

7.2.7

DTC Enable Registers A to H (DTCERA to DTCERH)

DTCER, which is comprised of eight registers, DTCERA to DTCERH, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 7.1. Use bit manipulation instructions such as BSET and BCLR to read or write a
DTCE bit. If all interrupts are masked, multiple activation sources can be set at one time (only at
the initial setting) by writing data after executing a dummy read on the relevant register.
Bit 15
Bit Name DTCE15
Initial Value 0
R/W R/W
Bit 7
Bit Name DTCE7
Initial Value 0
R/W R/W
Bit Bit Name
15 DTCE15
14 DTCE14
13 DTCE13
12 DTCE12
11 DTCE11
10 DTCE10
9 DTCE9
8 DTCE8
7 DTCE7
6 DTCE6
5 DTCE5
4 DTCE4
3 DTCE3
2 DTCE2
1 DTCE1
0 DTCE0
14 13
DTCE14 DTCE13
0 0
R/W R/W
6 5
DTCE6 DTCE5
0 0
R/W R/W
Initial
Value R/W Description
DTC Activation Enable 15 to 0
0 R/W
Setting this bit to 1 specifies a relevant interrupt source to
0 R/W
a DTC activation source.
0 R/W
[Clearing conditions]
0 R/W
•
•
0 R/W
0 R/W
•
0 R/W
These bits are not cleared when the DISEL bit is 0 and
0 R/W
the specified number of transfers have not ended
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Section 7 Data Transfer Controller (DTC)
12 11
DTCE12 DTCE11
0 0
R/W R/W
4 3
DTCE4 DTCE3
0 0
R/W R/W
When writing 0 to the bit to be cleared after reading 1
When the DISEL bit is 1 and the data transfer has
ended
When the specified number of transfers have ended
Rev.2.00 Jun. 28, 2007 Page 225 of 666
10 9
DTCE10 DTCE9
0 0
R/W R/W
2 1
DTCE2 DTCE1
0 0
R/W R/W
REJ09B0311-0200
8
DTCE8
0
R/W
0
DTCE0
0
R/W