Bus Cycles In Single Address Mode; Figure 7.33 Example Of Transfer In Single Address Mode (Byte Read) - Renesas H8SX/1500 Series Hardware Manual

7.4.11

Bus Cycles in Single Address Mode

(1)
Single Address Mode (Read and Cycle Stealing)
In single address mode, one byte, one word, or one longword of data is transferred at a single
transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the
CPU are executed in the bus released cycles.
In figure 7.33, the TEND signal output is enabled and data is transferred in bytes from the external
8-bit 2-state access space to the external device in single address mode (read).
Bφ
Address bus
RD
DACK
TEND

Figure 7.33 Example of Transfer in Single Address Mode (Byte Read)

DMA read DMA read
cycle
Bus
Bus
released
released
DMA read
cycle cycle
Bus
Bus
released
released
Rev. 3.00 Mar. 14, 2006 Page 191 of 804
Section 7 DMA Controller (DMAC)
DMA read
cycle
Bus
Last transfer
released
cycle
REJ09B0104-0300