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Bus release
Address
bus
DMA
Idle
control
Channel
Request
Minimum
of 2 cycles
[1]
[2]
[1]
Acceptance after transfer enabling; the
and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMA cycle is started.
[4] [7] Acceptance is resumed after the dead cycle is completed.
(As in [1], the
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Figure 7.25 Example of DREQ
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
7.5.10
DMA Transfer (Single Address Mode) Bus Cycles
Single Address Mode (Read): Figure 7.26 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state
access space to an external device.
1 block transfer
DMA
DMA
read
write
Transfer source
Transfer destination
Read
Write
Dead
Request clear period
[3]
Acceptance resumes
pin low level is sampled on the rising edge of , and the request is held.)
DREQ Pin Low Level Activated Block Transfer Mode Transfer
DREQ
DREQ
DMA
Bus
DMA
dead
release
read
Transfer source
Idle
Read
Write
Request clear period
Request
Minimum
of 2 cycles
[4]
[5]
[6]
pin low level is sampled on the rising edge of ,
Rev. 2.00, 05/03, page 257 of 820
1 block transfer
DMA
DMA
write
dead
Transfer destination
Dead
[7]
Acceptance resumes
Bus
release
Idle
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