Table 12.22 Minimum Number Of Idle Cycles Between Access Cycles Of The Dmac Single Address Mode For The Sdram Interface - Renesas HD6417641 Hardware Manual

Section 12 Bus State Controller (BSC)
Table 12.22 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single
Address Mode for the SDRAM Interface
(1) Transfer from the external device with DACK to the SDRAM interface
CMNCR.DMAIW
Setting
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. 4.00 Sep. 14, 2005 Page 396 of 982
REJ09B0023-0400
BSC Register Setting*
CS3WCR.WTRP
Setting
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
0
0
0
0
1
1
1
1
2
2
2
2
3
3
2
CS3WCR.TRWL
Setting
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
Minimum Number of
Idle Cycles
3
3
3
3
3
3
3
4
3
3
4
5
3
4
5
6
3
3
3
3
3
3
3
4
3
3
4
5
3
4