Basic Bus Interface; Data Bus; I/O Pins Used For Basic Bus Interface - Renesas H8SX/1650 Hardware Manual

6.6

Basic Bus Interface

The basic bus interface can be connected directly to the ROM and SRAM. The bus specifications
can be specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, CSACR, and ENDINCR.
6.6.1

Data Bus

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8)
or lower byte data bus (D7 to D0) is used according to the bus specifications for the area being
accessed (8-bit access space or 16-bit access space), the data size, and endian format when
accessing external address space. For details, see section 6.5.6, Endian and Data Alignment.
6.6.2

I/O Pins Used for Basic Bus Interface

Table 6.15 shows the pins used for basic bus interface.
Table 6.15 I/O Pins for Basic Bus Interface
Name
Bus cycle start
Address strobe
Read strobe
Read/write
Low-high write
Low-low write
Chip select 0 to 7
Wait
Note: * When the address/data multiplexed interface is selected, this pin only functions as the
AH output and does not function as the AS output.
Symbol I/O
BS
Output
AS*
Output
RD
Output
RD/WR Output
LHWR
Output
LLWR
Output
CS0 to CS7 Output
WAIT
Input
Function
Signal indicating that the bus cycle has started
Strobe signal indicating that an address output on the
address bus is valid during access
Strobe signal indicating the read access
Signal indicating the data bus input or output
direction
Strobe signal indicating that the upper byte (D15 to
D8) is valid during write access
Strobe signal indicating that the lower byte (D7 to
D0) is valid during write access
Strobe signal indicating that the area is selected
Wait request signal used when an external address
space is accessed
Rev.2.00 Jun. 28, 2007 Page 167 of 666
Section 6 Bus Controller (BSC)
REJ09B0311-0200