Timing Of Transition To Hardware Standby Mode - Renesas H8S Series Hardware Manual

Appendix F
F.1

Timing of Transition to Hardware Standby Mode

(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 system clock
cycles before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay
from STBY low to RES high: 0 ns or more).
STBY
RES
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained,
RES does not have to be driven low as in (1).
F.2 Timing of Recovery from Hardware Standby Mode
Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high to execute a
power-on reset.
STBY
RES
NMI
Timing of Transition to and Recovery from Hardware
Standby Mode
Figure F-1 Timing of Transition to Hardware Standby Mode
Figure F-2 Timing of Recovery from Hardware Standby Mode
≥10 t ≥0 ns
t t
1 cyc 2
t≥100 ns t
OSC
t
NMIRH
Rev.6.00 Oct.28.2004 page 1013 of 1016
REJ09B0138-0600H