Appendix E Pin States At Power-On - Renesas H8S Series Hardware Manual

Note that pin states at power-on depend on the state of the STBY pin and NMI pin. The case in which pins settle* from an
indeterminate state at power-on, and the case in which pins settle* from the high-impedance state, are described below.
After reset release, power-on reset exception handling is started.
Note: * "Settle" refers to the pin states in a power-on reset in each MCU operating mode.
E.1 When Pins Settle from an Indeterminate State at Power-On
When the NMI pin level changes from low to high after powering on, the chip goes to the power-on reset state*
high level is detected at the NMI pin. While the chip detects a low level at the NMI pin, the manual reset state*
established. The pin states are indeterminate during this interval. (Ports may output an internally determined value after
powering on.)
The NMI setup time (t
NMIS
Notes: 1. Applies to the ZTAT version only.
2. Except for the H8S/2357 ZTAT, all resets are power-on resets, regardless of the level on the NMI pin.
Figure E-1 When Pins Settle from an Indeterminate State at Power-On

Appendix E Pin States at Power-On

) is necessary for the chip to detect a high level at the NMI pin.
V
CC
STBY
1
Manual reset*
NMI
RES
φ
NMI = Low → NMI = High
Notes: 1. Applies to the ZTAT version only.
2. Except for the H8S/2357 ZTAT, all resets are
power-on resets, regardless of the level on the NMI pin.
t
OSC1
2
Power-on reset*
RES = Low
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