Tpc Output Mode Register (Tpmr) - Renesas F-ZTAT H8 Series Hardware Manual

11.2.10 TPC Output Mode Register (TPMR)

TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for
each group.
Bit 7
—
Initial value 1
Read/Write —
Group 3 non-overlap
Selects non-overlapping TPC
output for group 3 (TP
Group 2 non-overlap
Selects non-overlapping TPC
output for group 2 (TP
Group 1 non-overlap
Selects non-overlapping TPC
output for group 1 (TP to TP )
Group 0 non-overlap
Selects non-overlapping TPC
output for group 0 (TP to TP )
The output trigger period of a non-overlapping TPC output waveform is set in general register B
(GRB) in the ITU channel selected for output triggering. The non-overlap margin is set in general
register A (GRA). The output values change at compare match A and B. For details see section
11.3.4, Non-Overlapping TPC Output.
TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Section 11 Programmable Timing Pattern Controller
6 5
— —
1 1
— —
Reserved bits
to TP )
15 12
to TP )
11 8
7 4
3 0
4 3 2
— G3NOV G2NOV
1 0 0
— R/W R/W
Rev. 3.00 Mar 21, 2006 page 411 of 814
1 0
G1NOV G0NOV
0 0
R/W R/W
REJ09B0302-0300