Fig. 4.5.8 Da N Conversion Register; Fig. 4.5.9 Port P3 Output Mode Control Register - Renesas 7200 Series User Manual

M37220M3-XXXSP/FP
4.5 Functional description
DA n Conversion Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Fig. 4.5.8 DA n conversion register (addresses 00DE
Port P3 Output Mode Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 4.5.9 Port P3 output mode control register (address 00CD
4-18
DA n conversion register (DAn) (n = 1 and 2) [Address 00DE
B Name
0 DA conversion set
to bits
(DAn0–DAn5)
5
6 Fix this bit to "0."
7 Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is " 0."
16
Port P3 output mode control register (P3S) [address 00CD
B Name
0 P3 output structure
0
selection bit (P30S)
1 P3 output structure
1
selection bit (P31S)
2 DA1 output enable bit
(DA1S)
3 DA2 output enable bit
(DA2S)
4 Nothing is assigned. These bits are write disable bits.
to
When these bits are read out, the values are "0."
7
7220 Group User's Manual
Functions
b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 : 0/64Vcc
0 0 0 0 0 1 : 1/64Vcc
0 0 0 0 1 0 : 2/64Vcc
1 1 1 1 0 1 : 61/64Vcc
1 1 1 1 1 0 : 62/64Vcc
1 1 1 1 1 1 : 63/64Vcc
and 00DF )
16
Functions After reset R W
0 : CMOS output
1 : N-channel open-drain output
0 : CMOS output
1 : N-channel open-drain output
0 : P3 input/output
0
1 : DA1 output
0 : P3 input/output
1
1 : DA2 output
)
16
, 00DF ]
16 16
After reset R W
Indeterminate R W
0 R —
0 R —
]
16
0 R W
0 R W
0 R W
0 R W
0 R —