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3.3.2
Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3
Interrupt Control Registers
Register Name
IRQ edge select register*
Interrupt enable register 1*
Interrupt enable register 2*
Interrupt request register 1*
Interrupt request register 2*
Wakeup interrupt request register
Notes: 1. Write is enabled only for writing of 0 to clear a flag.
2. There are some differences in functions between the H8/3857 Group and the H8/3854
Group. For details, see the individual register descriptions.
IRQ Edge Select Register (IEGR)
Bit
Initial value
Read/Write
Note:
*
Applies to the H8/3857 Group. In the H8/3854 Group, this bit must always be cleared to
0.
IEGR is an 8-bit read/write register, used to designate whether pins IRQ
edge sensing or falling edge sensing.
Bits 7 to 5—Reserved Bits: Bits 7 to 5 are reserved; they are always read as 1, and cannot be
modified.
Edge Select (IEG4): Bit 4 selects the input sensing of pin IRQ
Bit 4—IRQ
4
Bit 4: IEG4
Description
Falling edge of IRQ
0
Rising edge of IRQ
1
Abbreviation
2
IEGR
2
IENR1
2
IENR2
2
IRR1
2
IRR2
IWPR
7
6
5
⎯
⎯
⎯
1
1
1
⎯
⎯
⎯
/ADTRG pin input is detected
4
/ADTRG pin input is detected
4
R/W
Initial Value
R/W
H'E0
R/W
H'00
R/W
H'00
1
R/W*
H'20
1
R/W*
H'00
1
R/W*
H'00
4
3
IEG4
IEG3
IEG2*
0
0
R/W
R/W
R/W
Rev.3.00 Jul. 19, 2007 page 75 of 532
3. Exception Handling
Address
H'FFF2
H'FFF3
H'FFF4
H'FFF6
H'FFF7
H'FFF9
2
1
IEG1
IEG0
0
0
R/W
R/W
to IRQ
are set to rising
0
4
/ADTRG.
4
(initial value)
REJ09B0397-0300
0
0
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