Interrupt Control Registers - Renesas H8 Series Hardware Manual

3.3.2

Interrupt Control Registers

Table 3.3 lists the registers that control interrupts.
Table 3.3 Interrupt Control Registers
Name
IRQ edge select register
Interrupt enable register 1
Interrupt enable register 2
Interrupt request register 1
Interrupt request register 2
Wakeup interrupt request register
Wakeup edge select register
Note: * Write is enabled only for writing of 0 to clear a flag.
IRQ Edge Select Register (IEGR)
Bit 7

Initial value 1

Read/Write
IEGR is an 8-bit read/write register used to designate whether pins
are set to rising edge sensing or falling edge sensing. For the IRQAEC pin edge sensing
specifications, see section 9.7, Asynchronous Event Counter (AEC).
Bits 7 to 5—Reserved
Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.
Abbreviation
IEGR
IENR1
IENR2
IRR1
IRR2
IWPR
WEGR
6 5 4
 
IEG4
1 1 0
 
R/W
Section 3 Exception Handling
R/W Initial Value
R/W —
R/W —
R/W —
R/W *
—
R/W *
—
R/W *
H'00
R/W H'00
3 2

IEG3 IEG1

0
R/W W R/W
, ,
I R Q I R Q
4 3
Rev. 7.00 Mar 10, 2005 page 79 of 652
Address
H'FFF2
H'FFF3
H'FFF4
H'FFF6
H'FFF7
H'FFF9
H'FF90
1 0
IEG0
0 0
R/W
, and
I R Q I R Q
1 0
REJ09B0042-0700