Interrupt Control Registers - Renesas M16C Series User Manual

M30240 Group

1.2.12.1 Interrupt control registers

Peripheral I/O interrupts have their own interrupt control registers. Table 1.11 shows the addresses
of the interrupt control registers. Figure 1.16 shows the interrupt control registers.
The interrupt request bit is set by hardware to "0" when an interrupt request is received. The interrupt
request bit can also be set by software to "0". (Do not set to "1".)
INT0 and INT1 are triggered by the edges of external inputs. The edge polarity is selected using the
polarity select bit. (Other interrupts are described elsewhere.)
An interrupt must first be enabled before it can be used to cancel stop mode.
Table 1.11: Addresses in interrupt control register
Interrupt control register
USB Suspend Interrupt
USB Resume interrupt
USB Start Of Frame
Bus collision detection
DMA0
DMA1
Key input interrupt
A-D
UART2 transmit
UART2 receive
UART0 transmit
UART0 receive
UART1 transmit
Rev.1.00 Sep 24, 2003 Page 30 of 360
Symbol
Address
name
0044
SUSPIC
16
0046
RSMIC
16
0047
SOFIC
16
004A
BCNIC
16
004B
DM0IC
16
004C
DM1IC
16
004D
KUPIC
16
004E
ADIC
16
004F
S2TIC
16
0050
S2RIC
16
0051
S0TIC
16
0052
S0RIC
16
0053
S1TIC
16
Interrupt control register
UART1 receive
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
USB Reset
INT0
INT1
USB Function
Interrupts
Symbol
Address
name
0054
S1RIC
16
0055
TA0IC
16
0056
TA1IC
16
0057
TA2IC
16
0058
TA3IC
16
0059
TA4IC
16
005A
TB0IC
16
005B
TB1IC
16
005C
RSTIC
16
005D
INT0IC
16
005E
INT1IC
16
005F
USBFIC
16