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2.3.11 Timer mode registers (address 00F4
The timer 12 mode register is assigned to address 00F4
address 00F5
. Both registers consist of 8 bits. They select the count source of timer and control the count
16
stop bit. Bits 5 to 7 of the timer 12 mode register and bits 6, 7 of the timer 34 mode register are not used.
2.3.12 CPU mode register (address 00FB
The CPU mode register is assigned to address 00FB
stack page. Set bits 0 and 1 are set to "0," and set bits 3 to 7 to "0."
2.3.13 Interrupt request registers (addresses 00FC
The interrupt request register 1 is assigned to address 00FC16 and the interrupt request register 2 is
assigned to address 00FD
Bits 3 and 5 to 7 of the interrupt request register 2 are not used.
2.3.14 Interrupt control registers (addresses 00FE
The interrupt control register 1 is assigned to address 00FE
to address 00FF
. Both registers consist of 8 bits, and sets enable/disable of interrupts.
16
Bits 7 to 5 and 3 of the interrupt control register 2 are not used.
2.3.15 2 page register (addresses 0217
(1) ROM correction addresses (address 0217
Addresses 0217
be corrected are set to the ROM correction addresses.
(2) ROM correction enable register (address 021B
The ROM correction enable register is assigned to address 021B
and controls the ROM correction function. Bits 2 to 7 are not used.
2.3.16 CRT display RAM (addresses 0600
The display RAM is used to specify the character to be displayed on the CRT and its color. Two addresses
are used for one character: one address (8 bits) to specify each character code and the other (8 bits) to
specify the color of the character.
2.3.17 ROM (addresses A000
The mask ROM is assigned.
In this internal ROM, addresses FFDE
vector area for reset and for interrupts. A vector jump destination storage address (16 bits) are stored in
2 addresses by the 1 interrupt source.
2.3.18 CRT display ROM (addresses 10000
The display ROM stores (masks) character patterns of each character to be displayed on the CRT. Although
one character consists of 16 (vertical) × 12 (horizontal) dots, it is divided into a 16 × 8 dot and a 16 × 4
dot pattern, with each pattern stored in one address. In other words, two addresses (16 bits) are used for
one character. The ROM can store up to 256 kinds of characters.
. Both registers consist of 8 bits, and hold content of each interrupt request bit.
16
to 021B
16
to 021A
are assigned to ROM correction address. The ROM data addresses to
16
16
to FFFF
)
16
16
, FFDF
16
7220 Group User's Manual
FUNCTIONAL DESCRIPTION
and 00F5
)
16
16
and the timer 34 mode register is assigned to
16
)
16
. This register consists of 8 bits, and specifies the
16
and 00FD
16
and 00FF
16
and the interrupt control register 2 is assigned
16
) (only M37221M8-XXXSP and M37221MA-XXXSP)
16
to 021A
)
16
16
)
16
to 06B7
)
16
16
, FFE4
, FFF5
16
16
16
to 11FFF
)
16
16
2.3 Memory assignment
)
16
)
16
. This register consist of 8 bits,
16
, and FFF8
to FFFF
16
are assigned to
16
2-19
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