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Register Name
Wake-up sense control register
Wake-up input interrupt status
register
Wake-up enable register
1. Address in the upper cell: when RELOCATE = 0, address in the lower cell: when
Note:
RELOCATE = 1
2. Address in the upper cell: when EIVS = 0, address in the lower cell: when EIVS = 1
5.3.1
Interrupt Control Registers A to D (ICRA to ICRD)
The ICR registers set interrupt control levels for interrupts other than NMI. The correspondence
between interrupt sources and ICRA to ICRD settings is shown in tables 5.2 and 5.3.
Bit
Bit Name
7 to 0 ICRn7 to ICRn0
Note: n: A to D
Abbreviation
WUESCR
WUESR
WER
Initial Value
R/W Description
All 0
R/W Interrupt Control Level
R/W
Initial Value Address
R/W
H'00
R/W
H'00
R/W
H'00
0: Corresponding interrupt source is interrupt
control level 0 (no priority)
1: Corresponding interrupt source is interrupt
control level 1 (priority)
Rev. 1.00 Apr. 28, 2008 Page 89 of 994
Section 5 Interrupt Controller
Data Bus
Width
H'FE84
8
H'FE85
8
H'FE86
8
REJ09B0452-0100
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