Interrupt Control Registers - Renesas H8/38024 Hardware Manual

3.3.2

Interrupt Control Registers

Table 3.3 lists the registers that control interrupts.
Table 3.3 Interrupt Control Registers
Name
IRQ edge select register
Interrupt enable register 1
Interrupt enable register 2
Interrupt request register 1
Interrupt request register 2
Wakeup interrupt request register
Wakeup edge select register
Note: * Write is enabled only for writing of 0 to clear a flag.
IRQ Edge Select Register (IEGR)
Bit

Initial value

Read/Write
IEGR is an 8-bit read/write register used to designate whether pins IRQ
are set to rising edge sensing or falling edge sensing. For the IRQAEC pin edge sensing
specifications, see section 9.7, Asynchronous Event Counter (AEC).
Bits 7 to 5—Reserved
Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.
Bit 4—IRQ Edge Select (IEG4)
4
Bit 4 selects the input sensing of the IRQ
Bit 4
IEG4 Description
Falling edge of IRQ
0
Rising edge of IRQ
1
Abbreviation
IEGR
IENR1
IENR2
IRR1
IRR2
IWPR
WEGR
7 6 5
 
1 1 1
 
4
and ADTRG pin input is detected
4
and ADTRG pin input is detected
4
R/W
R/W
R/W
R/W
R/W *
R/W *
R/W *
R/W
4 3
IEG4 IEG3
0 0
R/W R/W
pin and ADTRG pin.
Initial Value Address
— H'FFF2
— H'FFF3
— H'FFF4
— H'FFF6
— H'FFF7
H'00 H'FFF9
H'00 H'FF90
2 1

IEG1

0
W R/W
, IRQ , IRQ , and IRQ
4 3 1
(initial value)
Rev. 6.00, 08/04, page 77 of 628
0
IEG0
0
R/W
0